mirror of
https://github.com/JeffersGlass/DDS_VFO.git
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93 lines
3.4 KiB
C++
93 lines
3.4 KiB
C++
/*
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* si5351phase.ino - Example for setting phase with Si5351Arduino library
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*
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* Copyright (C) 2015 Jason Milldrum <milldrum@gmail.com>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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* Setting the phase of a clock requires that you manually set the PLL and
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* take the PLL frequency into account when calculation the value to place
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* in the phase register. As shown on page 10 of Silicon Labs Application
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* Note 619 (AN619), the phase register is a 7-bit register, where a bit
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* represents a phase difference of 1/4 the PLL period. Therefore, the best
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* way to get an accurate phase setting is to make the PLL an even multiple
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* of the clock frequency, depending on what phase you need.
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*
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* If you need a 90 degree phase shift (as in many RF applications), then
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* it is quite easy to determine your parameters. Pick a PLL frequency that
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* is an even multiple of your clock frequency (remember that the PLL needs
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* to be in the range of 600 to 900 MHz). Then to set a 90 degree phase shift,
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* you simply enter that multiple into the phase register. Remember when
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* setting multiple outputs to be phase-related to each other, they each need
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* to be referenced to the same PLL.
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*/
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#include "si5351.h"
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#include "Wire.h"
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Si5351 si5351;
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void setup()
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{
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// Start serial and initialize the Si5351
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Serial.begin(57600);
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si5351.init(SI5351_CRYSTAL_LOAD_8PF, 0);
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// We will output 14.1 MHz on CLK0 and CLK1.
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// A PLLA frequency of 705 MHz was chosen to give an even
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// divisor by 14.1 MHz.
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unsigned long long freq = 1410000000ULL;
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unsigned long long pll_freq = 70500000000ULL;
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// Set PLLA to the chosen frequency
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si5351.set_pll(pll_freq, SI5351_PLLA);
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// Set CLK0 and CLK1 to use PLLA as the MS source
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si5351.set_ms_source(SI5351_CLK0, SI5351_PLLA);
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si5351.set_ms_source(SI5351_CLK1, SI5351_PLLA);
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// Set CLK0 and CLK1 to output 14.1 MHz with a fixed PLL frequency
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si5351.set_freq(freq, pll_freq, SI5351_CLK0);
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si5351.set_freq(freq, pll_freq, SI5351_CLK1);
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// Now we can set CLK1 to have a 90 deg phase shift by entering
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// 50 in the CLK1 phase register, since the ratio of the PLL to
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// the clock frequency is 50.
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si5351.set_phase(SI5351_CLK0, 0);
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si5351.set_phase(SI5351_CLK1, 50);
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// We need to reset the PLL before they will be in phase alignment
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si5351.pll_reset(SI5351_PLLA);
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}
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void loop()
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{
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// Read the Status Register and print it every 10 seconds
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si5351.update_status();
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Serial.print("SYS_INIT: ");
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Serial.print(si5351.dev_status.SYS_INIT);
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Serial.print(" LOL_A: ");
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Serial.print(si5351.dev_status.LOL_A);
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Serial.print(" LOL_B: ");
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Serial.print(si5351.dev_status.LOL_B);
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Serial.print(" LOS: ");
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Serial.print(si5351.dev_status.LOS);
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Serial.print(" REVID: ");
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Serial.println(si5351.dev_status.REVID);
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delay(10000);
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}
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